1. Field of the Invention
The present invention relates to a data processor.
2. Description of the Prior Art
The address space at the conventional data processor, as shown in FIG. 1, comprises a memory storing therein programs and data; Internal registers in the processor are not mapped in the address space. In this case, it is required in accessing each register to use a particular instruction or specify the register, thereby not controlling each register in a unified manner and creating a problem in expansibility (problem 1).
Context switching of the conventional data processor is operated between the processor and a saving area in an external memory. In this case context switching takes much time. If the saving area is allotted to a particular high-speed memory to avoid this problem, the linearity of address space is deteriorated as shown in FIG. 2-(B) (problem 2).
Furthermore, in the conventional data processor, context switching is operated in batch with respect to all the contexts, thereby creating a problem in that even a register needless of switching is switched (problem 3).